- Clocks from 1 µHz to 2.05 GHz
- Random jitter less than 1 ps rms
- 16 digits of frequency resolution
- 80 ps rise and fall times
- CMOS, PECL, ECL, LVDS & RS-485
- Phase control and time modulation
- PRBS for eye-pattern testing
- OCXO and rubidium timebase
The CG635 generates
extremely stable square wave clocks between 1 µHz and 2.05 GHz.
The instrument's high frequency resolution, low jitter, fast transition
times, and flexible output levels make it ideal for use in the
development and testing of virtually any digital component, system
or network.
Clean clocks are critical in systems that use high-speed ADCs
or DACs. Spurious clock modulation and jitter create artifacts and
noise in acquired signals and in reconstructed waveforms.
CG635 Clock Generator
The CG635 generates extremely stable square wave
clocks between 1 µHz and 2.05 GHz. The instrument's high frequency
resolution, low jitter, fast transition times, and flexible output
levels make it ideal for use in the development and testing of virtually
any digital component, system or network.
Clean clocks are critical in systems that use high-speed ADCs or DACs.
Spurious clock modulation and jitter create artifacts and noise in
acquired signals and in reconstructed waveforms. Clean clocks are also
important in communications systems and networks. Jitter, wander, or
frequency offsets can lead to high bit error rates, or to a total loss
of synchronization. The CG635 can provide the clean, stable clocks
required for the most critical applications.
Output Drivers
The CG635 has several clock outputs. The front-panel Q and -Q
outputs provide complementary square waves at standard logic levels
(ECL, PECL, LVDS or +7 dBm). The square wave amplitude may also be set
from 0.2 V to 1.0 V, with an offset between -2 V and +5 V.
These outputs operate from DC to 2.05 GHz, have transition times of
80 ps, a source impedance of 50 Ω, and are intended to drive 50 Ω loads.
Output levels double when these outputs are unterminated.
The front-panel CMOS output provides square waves
at standard logic levels. The output may also be set to any amplitude
from 0.5 V to 6.0 V. The CMOS output has transition times of less than
1 ns and operates up to 250 MHz. It has a 50 Ω source impedance and is
intended to drive high impedance loads at the end of any length of 50 Ω
coax cable.
A rear-panel
RJ-45 connector provides differential square wave clocks on twisted pairs at RS-485
levels (up to 105 MHz) and LVDS levels (up to 2.05 GHz). This output
also provides ±5 VDC power for optional line receivers (CG640 to CG649).
The clock outputs have 100 Ω source impedances and are intended to
drive shielded CAT-6 cable with 100 Ω terminations.
The differential clocks may be used directly by the target system, or
with optional line receivers that provide complementary logic outputs on
SMA connectors.
